Part 6: A practical example - part 2 - VHDL coding Part 5: A practical example - part 1 - Hardware Testbench provide stimulus for design under test DUT or Unit Under Test UUT to check the output result. But that would be, to put it delicately, stupid.VHDL Testbench VHDL Testbench is important part of VHDL design to check the functionality of Design through simulation waveform. We can, of course, opt to test an IC after fabrication.

To start the process, select 'New Source' from the menu items under 'Project'. The Xilinx ISE environment makes it pretty easy to start the testing process. In this article I will continue the process and create a test bench module to test the earlier design.

The boilerplate also includes a stub for the main test process (tb:PROCESS, lines 72-81). The Wizard then creates the necessary boilerplate for a test bench module (see below).This article is available in PDF format for easy printingThe boilerplate includes the component declaration section (lines 38-58) and the instantiation of the test (lines 62-70). The 'New Source Wizard' then allows you to select a source to associate to the new source (in this case ClkDiv from the prior article), then click on 'Next'. From within the Wizard select 'VHDL Test Bench' and enter the name of the new module (click 'Next' to continue).

This sequence of steps creates a master clock signal of 40MHz.The next step is to establish the initial conditions for the device and to generate a reset pulse. This process waits a total of 25ns and then repeats. MCLK is driven low after the first 12.5ns and driven high after the next 12.5ns. The remaining lines (74-48) create a process that toggles the master clock (MCLK). This is done in the following code fragments.The first statement (line 60) defines a constant that is equal to half the period of the master clock. VHDL provides a simple way to create repetitive signal.

These statements are then repeated for each clock rate (remembering to increase the 'observation' wait time for each new clock rate)Now we can look at the completed results.At each clock selection point (toggling of RegStrb) we see a change in the outpur clock rate (Adc_Clk). We also need to allow time for the selected clock rate to be observed (i.e. The following code fragment shows these sequences.For each of the target clock rates we need to repeat the basic sequence of setting up the clock select register (Inbyte) and register select (RegSel) values and the toggling the RegStrb line (i.e. After the necessary delays (for RegStrb and allowing the clock divisor to run), we can repeat the sequence for each of the clock rates. So far, so good.The next step in the process is to write to the clock divisor (RegSel = '01', InByte = rate selection, RegStrb = '0' then RegStrb = '1'). At the first major timing mark (200ns) we can see SeqReset being driven high and the adc_clk soon starting to toggle (half period of 500ns, or the expected 1MHz rate).

In the previous article the ClkDiv process was written as:In testing, I found that I needed to correct the ClkDiv process to:It only goes to show, that if you haven't tested it, it probably doesn't work.In a future article, I will show some of the more advanced programming techniques of VHDL. During the generation of this test bench, I found that I had made a mistake in my earlier VHDL code (cut and paste, but no change in the data on line 48 and 50).

Testbench Generator Vhdl